1. Field of the Invention
This invention relates generally to Dynamic Random Access Memory (DRAM) integrated circuits, and more specifically, to a novel current-sensing amplifier for rapidly sensing memory cell state for low voltage, high density DRAM circuits.
2. Discussion of the Prior Art
As supply voltages are scaled down in DRAM technology, the voltage drive in a conventional cross-coupled latch required for a rapid sensing of memory cell state is correspondingly reduced. Current sensing is used commonly in SRAMs but proposals for its use in DRAMs have been limited and typically focused on high speed rather than low power (see, e.g., T. Blalock and R. Jaeger entitled xe2x80x9cA High-Speed Sensing Scheme for 1T Dynamic RAM""s Utilizing the Clamped Bit-Line Sense Amplifier,xe2x80x9d IEEE Journal of Solid State Circuits 27, 618 (1992)). The use of a reference transistor in the sub-threshold regime for DRAM sensing has been proposed by R. Dennard and R. Knepper in commonly-owned, co-pending U.S. patent application Ser. No. 09/777,004; with again an emphasis on high-speed rather than low voltage and low power. In the device described in aforementioned U.S. patent application Ser. No. 09/777,004, a small current is continuously drawn from the sense amplifier, thus resulting in increased power consumption.
The signal required in conventional voltage sensing is also a strong function of the capacitance of the bit line. Hence, the need to maintain an adequate noise margin severely restricts the number of cells that can be served by a single sense amplifier, thus limiting the array efficiency.
Another limitation to the array efficiency arises because a conventional cross-coupled latch sense amplifier operates using two complementary inputs. To eliminate common-mode noise, the two inputs are usually xe2x80x9cfoldedxe2x80x9d to lie on the same side of the sense amplifier. In such a folded bit line architecture, a passing word line is required, and a memory cell can be placed only at one-half of the crosspoints between word lines and bit lines. In the vertically folded (twisted) scheme, such as described in the reference by H. Hoenigschmid, et al., Symp. on VLSI Circuits, Dig. Tech. Papers, p. 125, June 1999, the two complementary inputs are constructed using different wiring levels twisted with each other so that the passing word line can be eliminated and a memory cell can be placed at every crosspoint.
However, the vertically folded bit line scheme still suffers from the drive and capacitance limitations discussed above, in addition to the additional complexity imposed by the additional wiring level.
In view of the aforementioned drawbacks, it would be highly desirable to provide a single input DRAM current sensing amplifier that includes a reference transistor biased in the sub-threshold regime to advantageously exploit its low impedance characteristic.
It would be further desirable to provide DRAM current sensing amplifier of low input impedance that includes a single bit-line input permitting a low voltage swing and enabling reduction of inter bit line coupling noise (low noise).
Moreover, it would be highly desirable to provide a single input DRAM current sensing amplifier with reduced sensitivity to bit line capacitance so more memory cells could be served with a single sense amplifier, thus improving array efficiency.
It would additionally be highly desirable to provide a single input DRAM current sensing amplifier for a DRAM memory cell that does not depend directly on supply voltage, thus maintaining speed as supply voltages are scaled down.
It would further be highly desirable to provide a single input DRAM current sensing amplifier for a DRAM memory cell that obviates the need for d.c. idling (quiescent) current thereby reducing power consumption requirements.
Additionally, it would further be highly desirable to provide a single input DRAM current sensing amplifier that allows placement of memory cells at every crosspoint of word and bit lines without complexity of additional wiring level (high array efficiency).
It is an object of the present invention to provide in a DRAM memory circuit, a current sensing amplifier of low input impedance that includes a single bit-line input permitting a low voltage swing and enabling reduction of inter bit line coupling noise (low noise).
It is a further object of the present invention to provide in a DRAM memory circuit, a current sensing amplifier with reduced sensitivity to bit line capacitance so more memory cells could be served with a single sense amplifier, thus improving array efficiency.
It is another object of the present invention to provide in a DRAM memory circuit, a single-input current sensing amplifier that advantageously exploits the low input impedance characteristic of a reference transistor biased in the sub-threshold regime.
It is still another object of the present invention to provide a single input DRAM current sensing amplifier for a DRAM memory cell that does not depend directly on supply voltage, thus maintaining speed as supply voltages are scaled down.
It is yet another object of the present invention to provide a single input DRAM current sensing amplifier for a DRAM memory cell that obviates the need for d.c. idling current thereby reducing power consumption requirements.
Yet, still another object of the present invention to provide a single input DRAM current sensing amplifier that allows placement of memory cells at every crosspoint without complexity of additional wiring level to thereby further increase array efficiency.
According to the principles of the invention there is provided a current sensing system and method for a memory circuit comprising an array of memory cells, each memory cell for storing a charge that is accessible by bit-line and a word-line, with a bitline having one or more cells connected thereto, the current sensing system comprising: a sense amplifier device for sensing a bit-line voltage, the sense amplifier device including a reference transistor having first, second and gate terminals, a first terminal defining an amplifier sense node, a second terminal for receiving a bit line input, and a gate terminal for receiving a reference voltage; a mechanism for preventing quiescent current flow through the reference transistor prior to a sensing operation, and enabling current flow through the reference transistor from a first voltage source during a sensing operation; a second voltage source for applying precharge voltage to the bit-line such that the reference transistor may be biased to a sub-threshold regime during a sense operation, wherein, upon accessing a memory cell during the sense operation, the reference transistor is biased to the sub-threshold regime for enabling a large voltage swing at the amplifier sense node depending upon a state of said memory cell, while exhibiting low bit-line voltage swing.
Advantageously, such a current-sensing amplifier according to the invention enables an increased number of cells to be served due to its weak dependence on bit-line capacitance. Additionally, the single-input nature of the amplifier eliminates the need for either a passing word line or an additional wiring level. If an additional bit-line wiring level is available, the current-sensing amplifier may be used in conjunction with a hierarchical bit-line scheme to further increase the number of cells served by each sense amplifier (very high array efficiency).